DS4425BN+【PDF 5/8 页】IC OSC CLOCK 425MHZ 10-LCCC

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Sheet目录1995

1页 2页 3页 4页 [5页]6页 7页 8页

DS4106/DS4212/DS4425

Pin Description

PIN

NAME

FUNCTION

Output Enable. On-chip pullup resistor. Connect OE to logic-high, VCC, or leave open to enable the

output clock. Connect OE to logic-low or GND to disable the output clock. The LVPECL output

clock is set to high impedance when disabled. The LVDS output clock is latched to a differential

high when disabled.

2, 7–10

N.C.

No Connection

GND

Ground

OUTP

Positive Clock Output, LVPECL or LVDS

OUTN

Negative Clock Output, LVPECL or LVDS

VCC

+3.3V Supply

—

Exposed Paddle. Do not connect this pad or place exposed metal under the pad.

OSCILLATOR

AMPLIFIER

PFD

COUNTER N

LOOP FILTER

VCO

COUNTER M

OUTPUT

BUFFER

VCC

OUTP

OUTN

GND

DS4106/

DS4212/

DS4425

Detailed Description

The DS4106/DS4212/DS4425 combine a crystal and an

IC to form a precision clock. Figure 1 shows a function-

al diagram of the devices. The IC consists of a crystal

oscillator, a low-noise PLL, selectable clock-divider cir-

cuitry, and an output buffer. The PLL consists of a digi-

tal phase/frequency detector (PFD) and low-jitter

generation VCO. The VCO signal is scaled by a clock-

divider circuit and applied to the output buffer.

Output Drivers

All devices are available with either LVPECL

(DS4106A/DS4212A/DS4425A) or LVDS (DS4106B/

DS4212B/DS4425B) output buffers. When not needed,

the output buffers can be disabled. When disabled, the

LVPECL output buffer goes to a high-impedance state.

However, the LVDS outputs go to a differential logic

one (OUTP latched high and OUTN latched low) when

the outputs are disabled.

Additional Information

For more available frequencies, refer to the DS4125

data sheet at www.maxim-ic.com/DS4125.

Figure 1. Functional Diagram

106.25MHz/212.5MHz/425MHz

Clock Oscillators

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